The present disclosure relates generally to semiconductor devices, and more specifically to the fabrication process of Fin field effect transistors (FinFETs) and methods of aligning approach more accurately during the fabrication process of FinFETs.
There are significant pressures on the semiconductor industry to enable smaller and smaller critical dimensions of integrated circuits. Fin field-effect transistors (FinFET) have smaller device sizes while with increased channel widths, which channels include the channels formed on the sidewalls of the fins and the channels on the top surfaces of the fins. To maximize the channel width of a FinFET, the FinFET may include multiple fins, with the ends of the fins connected to a same source and a same drain.
The fabrication process of integrated circuits (ICs) in general and FinFETs in particular include several stages, of which, the definition of a pattern associated with the circuit is of critical importance. The pattern may then be fabricated on a substrate using photolithography processes. Photolithographic methods typically include the use of successive resist layers that are latently imaged and subsequently developed and patterned over a substrate for purposes of fabricating any of several structures within the substrate. Successful semiconductor fabrication requires highly accurate alignment of features on masks used in photolithographic processes, and of their projection onto the wafer, such that successive mask-defined patterns of material are located on the wafer with accuracy in the low tens of nanometers range. The alignment process is never perfect; however, the overlay alignment measurement is critical for FET operation and must be tightly and measurably controlled during manufacture.
The front-end-of-line process (FEOL) denotes the first portion of IC manufacturing where the individual devices are patterned in the semiconductor. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers, which contains all processes of CMOS fabrication needed to form fully isolated CMOS elements. For example, a FEOL piece may include a semiconductor substrate, gates, source/drain regions, isolation regions, spacers, contacts, dielectric material, and first level metal interconnects.